A book by Bala Veluchamy

Actors are synthesizable finite-state machines.

A verification methodology built on the actor model — one authored artifact, carried from spec to silicon, that propagates through the SoC instead of restarting at every boundary.

The thesis

Verification tools change at every stage — a C model, then RTL, then a UVM testbench, then an emulator, then silicon — and each boundary is re-authored by hand, with the interpretation gap and verification debt that follow. This book carries one model of computation, the actor graph, across every boundary: it is a finite-state machine, finite-state machines synthesize, and so the same authored definition renders per substrate with no rewrite.

Companion code

The framework, rendered three ways

The actor framework in SystemVerilog, C++, and SystemC — plus every worked example from the book, browsable inline and downloadable. Same topology, three host languages.

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About

Bala Veluchamy

Written for the hardware design and verification engineer. The full book is free to read online; the paperback is available in print, and the PDF and code are free to download.

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